What Is Physical Address Space?

The physical address space encompasses the set of addresses that physical memory can occupy. The maximum size of the physical address space is determined by the number of bits of physical address that the CPU and chipset can decode. This size also establishes the theoretical maximum amount of physical memory (RAM) on the system.

As hardware has evolved, the number of address bits has increased, leading to larger physical address spaces and potentially greater amounts of RAM. Current x86 CPUs use 32, 36, or 40 bits for physical addresses in the modes that Windows supports, although the chipsets that are attached to some 40-bit processors limit the sizes to fewer bits. Current releases of 32-bit Windows support a maximum of 37 bits of physical address for use as general-purpose RAM (more may be used for I/O space RAM), for a maximum physical address space of 128 GB. (These values may increase in the future.) Windows also continues to support older processors that decode only 32 bits of physical address (and thus can address a maximum of 4 GB).

A processor that uses full 64-bit virtual addresses can theoretically address 16 exabytes. (An exabyte is a billion gigabytes, and a terabyte is a thousand gigabytes.) Current releases of 64-bit Windows support from 40 to 50 address bits and 128 GB to 1 terabyte of RAM, depending on the specific edition of the operating system.

The number of bits that are supported in physical addresses is important to driver writers because it establishes the range of destination addresses for DMA. Currently, drivers must be able to handle I/O transfers that use 37-bit physical addresses, and this number could increase in the future. For drivers that use the Windows DMA routines instead of the obsolete hardware abstraction layer (HAL) routines, increased address lengths are not a problem even if the device hardware supports only 32 address bits because the DMA routines perform any double-buffering that might be required to handle the addressing differences.

Some older drivers, however, do not use the Windows DMA routines. If such a driver assumes that its device will never be required to perform I/O to an address greater than 4 GB, it is likely to fail on some newer x86 platforms on which physical addresses can extend up to 128 GB. These drivers should be revised to use the Windows DMA routines.

The physical address space is used to address more than just RAM. It is also used to address all of the memory and some of the registers presented by devices. Consequently, if a machine is configured with the maximum amount of physical memory, some of that memory will be unusable because some of the physical address space is mapped for other uses.

Device memory and registers are mapped into the physical address space at address ranges that the chipset controls. Memory locations are read and written through LOAD and STORE instructions; in the x86 assembly language, load and store are implemented through the MOV instruction.

Although some device registers are mapped into the physical address space, others are I/O space instead, depending on the design of the device hardware and the chipset in the individual machine. I/O space is a holdover from the early days of microprocessors when memory was a limited resource and few devices had their own addressable memory. Creating a separate, limited address space through which to address device registers saved important main memory space for the operating system and applications.

On the hardware platforms that Windows currently supports, I/O space is implemented as a separate 64‑KB physical address space. Locations in I/O space are read and written through IN and OUT instructions.

The addresses that are used to identify locations in a physical address space are often called physical addresses. However, this term can sometimes be confusing because not all physical addresses are alike—every physical address identifies a location relative to the bus on which it is placed. The following terms more precisely describe the physical addresses:

·         Processor-relative physical addresses

·         Device-bus relative physical addresses

Understanding which type of physical address each component uses can help you ensure that your driver uses the correct type of address for each context. Figure 3 shows the types of addresses used by various system components. In the figure:

·         The light gray area at the top shows the virtual address space.

·         The unshaded area shows the operating system and drivers, which can use either virtual addresses or physical addresses, depending on the situation.

·         The darker gray areas at the bottom show components that use physical addresses. The components in the lighter area use processor-relative physical addresses, and those in the darker area use device bus-relative physical addresses.

Figure 3. Physical addresses

The following sections describe processor-relative and device-bus-relative physical address in more detail.

Processor-Relative Physical Addresses

A processor-relative physical address is an address that the CPU places on the CPU bus. This address identifies a location in the physical memory space, which contains all addresses that can be the target of a MOV instruction. When the memory manager and the CPU translate a virtual address to a physical address, the result is a processor-relative physical address.

After the CPU issues an instruction with a processor-relative physical address, the memory controller (also called the North Bridge) decodes the address and directs it appropriately. If the address identifies a location in physical memory, the memory controller, in theory, translates it to the specific location relative to the memory bus at which the memory is located. On standard PC platforms, however, the processor-relative physical address is almost always the same as the address in physical memory space, so the translation is simply a one-to-one identity mapping.

If the address identifies a location that is mapped to a device, the memory controller translates it to a device-bus-relative physical address. It can then place the translated address on the appropriate bus.

Device-Bus-Relative Physical Addresses

The device-bus relative address space defines a set of addresses that identify locations on a specific bus.

Note

The Windows DDK uses the term “logical address space” to describe the device-bus relative address spaces and the term “logical address” to describe an address that is used to identify a location in them. Like “physical address,” these terms are sometimes confusing because they are often used in other contexts and with other meanings.

In theory, each device bus can have its own address space. In practice, however, most PC platforms implement only a single root device bus. The few platforms that implement more than one root device bus simply segment the available address space without translating it, so that all the root buses appear to share a single address space.

In addition, the PCI Specification defines the relationship between the address spaces of parent and child PCI buses and prohibits translations. Any translations that are performed in such machines must take place at the level of the root device bus.  

When a device receives a device-bus-relative address, it decodes the address to determine whether the bus cycle is intended for it and, if so, for which of its registers.

Devices issue device-bus relative physical addresses when they perform DMA. These addresses are later translated to processor-relative physical addresses (typically by the memory controller). The map registers that are central to the Windows DMA model are essentially an abstraction of this translation step. The use of map registers ensures that any device can perform DMA to any location in physical memory, regardless of any addressing limitations in the device. Depending on the individual machine, the map registers might be implemented in hardware or in software.